As shown in FIG. 1, a multiple PWM regulator system includes multiple PWM regulators 10 to convert an input voltage Vin to multiple output voltages Vo1-VoN, respectively, and a decoupling capacitor Cde coupled to the voltage input terminal Vin to reduce the ripples of the input voltage Vin. Each of the PWM regulators 10 has a PWM controller 12 responsive to a respective clock to trigger a pulse width modulation signal PWM to drive a power stage 14 to convert the input voltage Vin to the output voltage. Due to each of the PWM regulators 10 having a respective clock, noise perceptible to the human ear will be produced if the multiple clocks have any frequency difference between 20 Hz and 20 KHz.
In a multiple PWM regulator system, clock synchronization is an approach to well control the noise caused by the frequency difference between the multiple clocks. As shown in FIG. 2, a clock synchronized multiple PWM regulator system uses a same clock for all the PWM regulators 10 to trigger the pulse width modulation signals PWM and as a result, as shown by the waveform 16 at time t1 in FIG. 3, large ripple is produced in the input voltage Vin since all the pulse width modulation signals PWM are simultaneously switched on/off, which will cause electro-magnetic interference (EMI) issue and may damage the PWM regulators 10.
It is feasible to reduce the ripple of the input voltage Vin by increasing the decoupling capacitance Cde; however, costs are increased consequently. In order to reduce the Vin decoupling capacitance Cde, there are some approaches, such as phase locked loop (PLL), to achieve interleaved phase between the multiple PWM regulators with interleaved clock synchronization. As shown by the stackable master/slave scheme of FIG. 4, a master PWM regulator 20 provides clocks CLK2-CLKN for slave PWM regulators 22. The slave PWM regulator 22 has the same circuit as that of the PWM regulator 10 shown in FIG. 1, while the master PWM regulator 20 further includes a phase shift control logic 24 to shift the clock CLK1 of the master PWM regulator 20 to generate the clocks CLK2-CLKN for the slave PWM regulators 22. As shown by the waveform 26 of FIG. 5, clock interleaved can reduce the Vin ripple without increasing the Vin decoupling capacitance Cde.
There have been proposed many methods for interleaved phase shift clock synchronization. For example, U.S. Pat. No. 7,493,504 uses PLL and external setting to extract different phase. However, PLL costs large cost penalty for integrated circuit (IC) and makes the circuit more complicated. U.S. Pat. No. 7,259,687 discloses a system and method for distributing phase information, in which a master PWM regulator provides a source current for a resistor network to generate a plurality of voltages applied to a plurality of slave PWM regulators, respectively, and each of the slave PWM regulators compares the received voltage with a plurality of preset values to determine its relative position and actuation timing. For example, a received voltage between first and second preset values indicates that the PWM regulator receiving this voltage is the first slave PWM regulator and likewise, a received voltage between second and third preset values indicates that the PWM regulator receiving this voltage is the second slave PWM regulator. The other slave PWM regulators are also identified in the same way. However, the quantity of the preset values determines the maximum number of PWM regulators allowed in a multiple PWM system, which makes the application lack of flexibility.
Therefore, it is desired a simple method for interleaved phase shift clock synchronization that allows an arbitrary number of PWM regulators to establish a multiple PWM system.